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Cascade Lake W - Cores - Intel
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Cascade Lake W
cascade-lake-w (front).png
General Info
DesignerIntel
ManufacturerIntel
IntroductionOctober 7, 2019 (announced)
October 7, 2019 (launched)
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformGlacier Falls
Word Size
8 octets
16 nibbles
64 bit
Process14 nm
0.014 μm
1.4e-5 mm
Packaging
PackageFCLGA-2066 (LGA)
Dimension52.5 mm × 45 mm
Pitch1.016 mm
Contacts2066
SocketSocket R4
Succession

Cascade Lake W (Cascade Lake Workstations; CLS-W) is codename for Intel's enterprise workstation microprocessor line based on the Cascade Lake microarchitecture, succeeding Skylake W. Cascade Lake W processors feature a number of enhancements including a new AVX512 x86 extension for neural network / deep learning workloads. Cascade Lake W series of processors are branded as the Xeon W family.

Overview[edit]

Cascade Lake W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the Lewisburg chipset. All processors are socket FCLGA-3647, manufactured on Intel's enhanced 14++ nm process based on the Skylake microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as vPro, Volume Management Device (VMD), and RAS.

Common Features[edit]

For the most part, Cascade Lake W processors come with all the features enabled and only core count and frequency being the differentiating feature. It's worth pointing out that the Skylake W come with AVX-512 along with two full execution units, similar to the high-end Skylake SP models (with the exception of the two low-end models). All models have 48 PCIe lanes and have all the following features in common:

Cascade Lake W Processors[edit]

Note that for the lower core-count models, the L3 cache size is larger than it would otherwise be due to additional cache slices being enabled from disabled cores.

 List of Cascade Lake W-based Processors
ModelLaunchedPriceCoresThreadsTDPL2L3FrequencyTurboTurbo Max
Count: 0

See also[edit]

arrow up 1.svgPower/Performance

designerIntel +
first announcedOctober 7, 2019 +
first launchedOctober 7, 2019 +
instance ofcore +
isax86-64 +
isa familyx86 +
main imageFile:cascade-lake-w (front).png +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake W +
packageFCLGA-2066 +
platformGlacier Falls +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket R4 +
word size64 bit (8 octets, 16 nibbles) +